Compiler Design Books - Page 4

MMIXware: A RISC Computer for the Third Millennium

Donald E. Knuth

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Editorial Review:

MMIX is a RISC computer designed by Don Knuth to illustrate machine-level aspects of programming. In the author's book series "The Art of Computer Programming", MMIX replaces the 1960s-style machine MIX. A particular goal in the design of MMIX was to keep its machine language simple, elegant, and easy to learn. At the same time, all of the complexities needed to achieve high performance in practice are taken into account. This book constitutes a collection of programs written in CWEB that make MMIX a virtual reality. Among other utilities, an assembler converting MMIX symbolic files to MMIX objects and two simulators executing the programs in given object files are provided. The latest version of all programs can be downloaded from MMIX's home page. The book provides a complete documentation of the MMIX computer and its assembly language. It also presents mini-indexes, which make the programs much easier to understand.

Compiler Design and Construction

A. Pyster

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Customer Reviews:
Total reviews: 1 Average rating: 5.0 of 5

A gem 5 out of 5 stars.
0 of 0 people found this review helpful.

I've owned this book for quite some time and have always meant to write a review about it, but for one reason or another have always blown it off. The time has come, however to give full credit to good old Doc. Pyster. First off, this little book (a mere 357 pages including index,appendix,et al)concisely explains not only theoretical concerns but practical implementations as well. Pyster shows you,step by step, the implementation of a robustly featured Pascal compiler(called Rascal)using a LL(1) grammar. One of the beautiful features of this compiler description is the definition of an Expression that includes not only a leading minus sign but a plus/minus sign anywhere allowed by the conventions of Mathematics. I have a number of compiler development books(including the much cited Dragon book)and they all define expressions with optional leading minus signs (ex. -5 +3*2)but not expressions of the form(-5+-5*2). That second -5 is just not allowed for. Not so with Doc. Pyster. His CFG fully allows unary minus' anywhere that traditional mathematical analysis allows.

I don't know if any of you Amazonians have taken a Compiler development course or worked in the field, but you should recognize that it's exceedingly difficult to write a cfg specifying a computer language. Any help you can get from books is appreciated.pyster's fills that bill.

Compilation Techniques for Reconfigurable Architectures

João M.P. Cardoso, Pedro C. Diniz

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Editorial Review:

This book describes a wide range of code transformations and mapping techniques for compiling programs written in high-level programming languages to reconfigurable architectures. While many of these transformations and mapping techniques have been developed in the context of compilation for traditional architectures and high-level synthesis, their application to reconfigurable architectures poses a whole new set of challenges- particularly when targeting fine-grained reconfigurable architectures such as contemporary Field-Programmable Gate-Arrays (FPGAs).

Organized in eight chapters, this book provides a helpful structure for practitioners and graduate students in the area of computer science and electrical and computer engineering to effectively map computations to reconfigurable architectures.

Key Features:

• Introduces the reader to hardware compilation and reconfigurable computing architectures.
• Presents a range of compiler code transformations and mapping techniques focusing on imperative programming languages.
• Allows the reader to bridge the gap between the software compilation and the hardware compilation and synthesis domains.
• Brings a number of compilation techniques together into one structured source, and includes representative examples of their applications.

• Provides a historical perspective on representative compilation research efforts over the last 15 years.

Programming Languages: An Active Learning Approach

Kent Lee

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Editorial Review:

Programming Languages: An Active Learning Approach introduces students to three programming paradigms: object-oriented/imperative languages using C++ and Ruby, functional languages using Standard ML, and logic programming using Prolog. This interactive textbook is intended to be used in and outside of class. Each chapter follows a pattern of presenting a topic followed by a practice exercise or exercises that encourage students to try what they have just read. This textbook is best-suited for students with a 2-3 course introduction to imperative programming.

 

Key Features:

• Accessible structure guides the student through various programming languages
• Seamlessly integrated practice exercises
• Classroom-tested
• Online support materials

 

Advance Praise for Lee’s Programming Languages: An Active Learning Approach

"The Programming Languages book market is overflowing with books, but none like this. In many ways, it is precisely the book I have been searching for to use in my own programming languages course. One of the main challenges I perpetually face is how to teach students to program in functional and logical languages, but also how to teach them about compilers. This book melds the two approaches very well."

-- David Musicant, Carleton College

 

The Cray X-MP/Model 24: A Case Study in Pipelined Architecture and Vector Processing (Lecture Notes in Computer Science)

Kay A. Robbins, Steven Robbins

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Editorial Review:

This book examines the issues relevant to the design of vector and pipelined computer systems using the Cray X-MP/24. The purpose of the book is to help the readers arrive at a deep understanding of how vector processing systems really work. These insights will be useful to the scientist who would like to obtain maximum performance from a vector machine, to the computer science student, and to the compiler writer. The book can also be used to supplement a regular textbook in a graduate or senior level course in computer architecture. The book looks at the overall design of the Cray X-MP and then explores the operation of the machine by looking at detailed timings of various instructions and code segments. It examines such issues as instruction issues and buffering, handling of jump instructions, use of registers to hold intermediate results, memory conflicts resulting from vectorization, optimal vectorization of multiple statement loops, and synchronization problems with multi-tasking. Detailed Gantt charts are provided to guide the reader through the timing issues.

Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler and Primetime

Himanshu Bhatnagar

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Editorial Review:

Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® and PrimeTime® describes the advanced concepts and techniques used for ASIC chip synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.
The emphasis of this book is on real-time application of Synopsys tools used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-arounds described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solutions.
Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® and PrimeTime® is intended for anyone who is involved in the ASIC design methodology, starting from RTL synthesis to final tape-out. Target audiences for this book are practicing ASIC design engineers and graduate students undertaking advanced courses in ASIC chip design and DFT techniques.
From the Foreword:
`This book, written by Himanshu Bhatnagar, provides a comprehensive overview of the ASIC design flow targeted for VDSM technologies using the Synopsis suite of tools. It emphasizes the practical issues faced by the semiconductor design engineer in terms of synthesis and the integration of front-end and back-end tools. Traditional design methodologies are challenged and unique solutions are offered to help define the next generation of ASIC design flows. The author provides numerous practical examples derived from real-world situations that will prove valuable to practicing ASIC design engineers as well as to students of advanced VLSI courses in ASIC design'.
Dr Dwight W. Decker, Chairman and CEO, Conexant Systems, Inc., (Formerly, Rockwell Semiconductor Systems), Newport Beach, CA, USA.

Static Analysis: 15th International Symposium, SAS 2008, Valencia, Spain, July 16-18, 2008, Proceedings (Lecture Notes in Computer Science)

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Editorial Review:

This book constitutes the refereed proceedings of the 15th International Symposium on Static Analysis, SAS 2008, held in Valencia, Spain in July 2008 - co-located with LOPSTR 2008, the International Symposium on Logic-based Program Synthesis and Transformation, PPDP 2008, the International ACM SIGPLAN Symposium on Principles and Practice of Declarative Programming, and PLID 2008, the International Workshop on Programming Language Interference and Dependence.

The 22 revised full papers presented together with two invited lectures were carefully reviewed and selected from 63 submissions. The papers address all aspects of static analysis including abstract domains, abstract interpretation, abstract testing, compiler optimizations, control flow analysis, data flow analysis, model checking, program specialization, security analysis, theoretical analysis frameworks, type based analysis, and verification systems.

A Compiler Generator for Microcomputers

Peter Rechenberg, Hanspeter Mossenbock

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Retargetable Compiler Technology for Embedded Systems - Tools and Applications

Rainer Leupers, Peter Marwedel

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Editorial Review:

It is well known that embedded systems have to be implemented efficiently. This requires that processors optimized for certain application domains are used in embedded systems. Such an optimization requires a careful exploration of the design space, including a detailed study of cost/performance tradeoffs. In order to avoid time-consuming assembly language programming during design space exploration, compilers are needed. In order to analyze the effect of various software or hardware configurations on the performance, retargetable compilers are needed that can generate code for numerous different potential hardware configurations. This book provides a comprehensive and up-to-date overview of the fast developing area of retargetable compilers for embedded systems. It describes a large set important tools as well as applications of retargetable compilers at different levels in the design flow. Retargetable Compiler Technology for Embedded Systems is mostly self-contained and requires only fundamental knowledge in software and compiler design. It is intended to be a key reference for researchers and designers working on software, compilers, and processor optimization for embedded systems.

A WCET-Aware Compiler- Design, Concepts and Realization

Paul Lokuciejewski

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Editorial Review:

In contrast to general-purpose systems, the correctness of real-time systems not only depends on the logical results of the computation but also on its temporal behavior specified by the worst-case execution time (WCET). Nowadays, software for embedded systems acting as real-time systems is written in high-level languages requiring the presence of a compiler. Modern compiler optimizations aim at reducing the program's average-case execution time completely ignoring the WCET. Tuning an application with respect to its worst-case execution time must be performed manually. To avoid this tedious and error-prone approach, an automation by the compiler is highly desired. This book faces this issue and describes the integration of a timing analyzer into a compiler infractructure. It presents flexible concepts describing the design and realization of a novel WCET-aware C compiler. Due to the combination of the extensive compiler knowledge on the program and the timing information, this compiler framework is best suited for the development of WCET-aware compiler optimizations. This book is intended for students but also for any reader interested in the construction of real-time compilers.